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GlobalFoundries announces new 7nm FinFET process, full node shrink

GlobalFoundries has had a rough few years. The company’s initial 28nm rollout was well behind schedule and its 14nm technology (originally called 14XM) was cancelled in favor of licensing Samsung’s 14nm LPE / LPP. Currently, GF serves as the second-source manufacturer for Apple products, builds AMD’s 14nm Polaris GPU family, and is expected to build AMD’s upcoming Zen processor (this has not been confirmed, but GF has always built AMD’s “big-core” CPUs). Now, GlobalFoundries is taking another shot at building out its own custom process technology, with an announcement that it intends to skip the 10nm node entirely and bring its own 7nm product to market. Even more interesting is the fact that the company intends to execute a full node shrink at 7nm, rather than using a hybrid node.

A quick word on “full node” versus “hybrid node.” We’ve used these terms for several years now, but I’m not sure I’ve ever actually explained what they mean. Semiconductor manufacturing can be broken (very generally) into three steps: FEOL (front-end-of-line), BEOL (back-end-of-line), and packaging. Samsung and TSMC both use hybrid nodes at 14/16nm, though Samsung’s 14nm is actually based on an unreleased 20nm die-shrink.

FEOL covers wafer production, lithography, etch, and deposition. Broadly speaking, FEOL refers to the process of manufacturing transistors. Both Samsung/GlobalFoundries and TSMC decided that the major differentiating feature of 14/16nm would be the introduction of FinFET technology (FinFETs are literal “fins” that stick up from the transistor and provide superior performance compared with conventional 2D planar technology. For more information on FinFETs, see this article).

Once the individual components of a chip have been created, they have to be connected together. BEOL refers to this process. The metal layers, insulating layers, vias, and bond sites are all added during this phase.

When we say that TSMC and Samsung are using a hybrid node, it means they are combining a new transistor architecture (or smaller transistors) with an already-established set of design rules for how those transistors are connected together. Shrinking or modifying FEOL and BEOL at the same time is a full node. It’s important to note that just because a node is hybridized doesn’t make it bad — one advantage to the hybrid node process is that the foundry and its customers can tackle one set of challenges at a time, rather than trying to pull off the more difficult task of scaling their entire design process at once.

To-date, only Intel has stuck to the goal of executing full-node shrinks at every new technology introduction. GlobalFoundries wants to copy this process at the 7nm node, and will be skipping 10nm in favor of doing so. It’s also explicitly not licensing Samsung technology this time around.

Right now, GF is projecting that its 7nm node will offer 30% improved performance over today’s 14/16nm with double the transistor density. GF will upgrade its Saratoga County foundry in New York State to handle the new node.

“The industry is converging on 7nm FinFET as the next long-lived node, which represents a unique opportunity for GlobalFoundries to compete at the leading edge,” said GlobalFoundries CEO Sanjay Jha. “We are well positioned to deliver a differentiated 7nm FinFET technology by tapping our years of experience manufacturing high-performance chips, the talent and know-how of our former IBM Microelectronics colleagues, and the world-class R&D pipeline from our research alliance. No other foundry can match this legacy of manufacturing high-performance chips.”

There’s no word on whether this new 7nm node will incorporate silicon germanium,(SiGe), a material that’s been floated as a possible enhancement for cutting-edge lithography. The company also stopped short of promising an EUV deployment at 7nm, though it noted that its process node will be compatible with EUV “at key levels.” That’s probably wise — EUV has been delayed so often and so long that there’s no firm deadline for integrating it into modern lithography, despite the clear need for a next-generation solution.

The implications we’ve heard from TSMC are that 10nm, like 20nm, may be a relatively short-term node. Some have suggested that this will be a hybrid 10/20 line rather than a 10/14 for TSMC, but even this is less than clear. If 10nm is indeed short-lived, it makes sense for GF to start working on a 7nm full node shrink now. The company has also announced that it will build a 12nm fully-depleted SOI node, though this is apparently for memory and embedded customers. There’s no sign that AMD or other major logic producers intend to use FD-SOI as opposed to FinFET technology for next-generation high-end CPUs or SoCs. If GF can pull the node off, it would increase competition at cutting-edge nodes and take semiconductor manufacturing from a two-way race into a three-way competition.

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